Sigma-delta ADCs and digital-to-analog converters ("DACs") have recently come into widespread use with the development of suitable process technology and the increase in digital audio and other applications. Sigma-delta converters utilize oversampling techniques (i.e., sampling at rates greater than the Nyquist rate) to achieve high signal-to-noise ratios. Such converters also exhibit excellent linearity. Additionally, sigma-delta converters are relatively straight-forward and inexpensive to implement due to their simplicity.
A sigma-delta ADC converts an analog input voltage to digital output samples at a predetermined rate. A typical sigma-delta ADC includes a front-end modulator which, by performing an oversampling technique referred to as "noise shaping", manipulates the noise spectrum of the analog input signal such that a major component of the quantization noise power is shifted to a frequency range outside of the band of interest, which is typically the signal band width (within the output samples). Subsequent filtering ("decimation") is performed in the digital domain to reduce the out-of-band quantization noise component of the digital output samples.
A conventional, first order low-pass sigma-delta ADC is shown in block diagram form in FIG. 1. The ADC includes a modulator 50 and a decimator 60. Modulator 50 converts an input voltage Vin, received on line 70, into a one-bit data stream X at a rate determined by the sampling frequency Kf.sub.s. Modulator 50 performs oversampling and noise shaping on the input voltage. The one-bit data stream X is provided on line 59 to decimator 60 which low-pass filters the data stream to reduce the quantization noise component thereof, and provides filtered output samples at a rate f.sub.s on output line 61. In short, the decimator 50 decimates, by a factor K, the one-bit data stream.
The modulator 50 includes an input circuit 51 which samples the input voltage Vin and provides the sampled input signal to a summing circuit 54. Summing circuit 54 subtracts a feedback signal (described below), received on line 65, from the sampled input signal and provides the output signal difference on line 55 to an integrator 56. Integrator 56 conventionally "integrates" the output signal difference from the summing circuit 55 and provides an output voltage A to a clocked, latched comparator 58. Summing circuit 54 can generally be considered as an input section of the integrator. Comparator 58 conventionally "compares" voltage A to a reference voltage and provides an output X at a rate Kf.sub.s (corresponding to its clock), which output X is the one-bit data stream output of the modulator. Thus, comparator 58 is effectively a one-bit ADC.
Data stream X is also provided on feedback line 63 to a feedback circuit 52, which includes a one-bit DAC. The output X controls a switch 53 within the feedback circuit 52 such that either a positive feedback reference voltage +Vref, received on line 74, or a negative feedback reference voltage -Vref, received on line 76, will be applied, for each bit, via feedback line 65, to the summing circuit 54. This switching operation of the feedback circuit 52 of the modulator 50 is conventional for a closed-loop circuit and should be readily understood by those skilled in the art.
Integrator 50 typically includes an operational amplifier and a feedback connected capacitor (not shown in FIG. 1). The above description of the modulator, in which a single input voltage is sampled (with respect to ground), assumes the use of a single-ended operational amplifier. As will be understood by those skilled in the art, however, the integrator may include a differential amplifier for which positive and negative input voltages are separately sampled.
Switched-capacitor circuits are commonly used to implement the input and feedback circuits for respectively sampling the input and feedback reference voltages. Switched-capacitor circuits include switches and capacitors. During operation, a capacitor is typically charged by a voltage source (i.e., the input voltage or feedback reference voltage source) through a first switch (or switches) during a first time interval (clock phase), and charge is thereafter "transferred" during the closing of a second switch (or switches) from the capacitor during a second, non-overlapping time interval. The switches often include CMOS transistors due to their high performance and yield.
What is described is a first order modulator that does not suffer input overload until Vin&gt;Vref. Sooch applies to higher order modulators as does the present invention.
When the level of the analog input voltage of an ADC modulator applied to the integrator input approaches the level of either the positive feedback reference voltage or the negative feedback reference voltage applied to the integrator input (such a condition is sometimes referred to as "input overload" or "crash"), the noise level in the digital output samples greatly increases. Such a condition is described and addressed, for example, in U.S. Pat. No. 4,851,841 to Sooch. The noise increase occurs during an input overload situation because the modulator output remains in the same state for a relatively long number of clock cycles and, thus, an even longer period of time is needed to stabilize the integrator output and achieve an accurate output. In fact, complete modulator instability may result from an extreme input overload situation. With higher-order modulators (which include a greater number of integrators), the risk of instability increases and the input voltage range over which the modulator remains stable decreases.
"Gain scaling" is an approach aimed at reducing the risk of modulator instability due to the above-described input voltage overload condition. Gain scaling typically involves "ratioing" the value of the input capacitor or resistor (used to sample the input voltage) to the value of the feedback capacitor or resistor (used to sample the feedback reference voltage) such that the charge "transferred" to the integrator capacitor from the feedback capacitor will be greater (by a predetermined factor) than that transferred from the input capacitor. It should be appreciated by those skilled in the art that, as used in the art and herein, charge "transfer" refers to a charging of the integrator capacitor by the integrator output voltage source to compensate for the charging or discharging of the input or feedback capacitors (explained in greater detail hereinafter). Thus, a literal, physical movement of charge may not occur.
The increase in transferred feedback charge appears to the integrator as if the input voltage has been attenuated relative to the feedback--i.e., some dynamic range is lost. The seeming "attenuation" in input voltage is usually compensated for in the digital domain by providing gain (e.g., in an amount to compensate for the attenuation factor). Such a gain scaling technique is described, for example, in the Sooch patent. While the capacitor (or resistor) ratioing approach has generally satisfactory performance, it requires the use of capacitors (or resistors) of different values for sampling the input signal and the feedback signal; this may necessitate pre-operation gain calibration of the modulator.
U.S. Pat. No. 5,134,401 to McCartney, while not expressly aimed at gain scaling, teaches that input voltage gain or attenuation (of a sigma-delta modulator) can be achieved without ratioing the values of the input and feedback capacitors (or resistors). Rather, the modulator of the McCartney patent adjusts the rate of sampling of the input voltage relative to the rate of sampling of the feedback reference voltage to achieve a desired input voltage gain or attenuation. For input voltage attenuation, for example, the McCartney patent teaches to sample the input voltage during only one time clock phase and to sample the feedback reference voltage during both clock phases, thus transferring feedback signal charge at twice the rate of the transfer of input signal charge. While the approach taught in the McCartney patent has generally satisfactory performance, it requires sampling the input signal at a lesser rate than sampling the feedback reference signal to achieve gain scaling.
Accordingly, a general object of the present invention is to provide a high-performance sigma-delta ADC including circuitry for preventing modulator instability due to an input voltage overload condition which avoids the design constraints of the prior art.